1. Field of the Invention
The invention relates to a static memory apparatus and more particularly relates to a data reading method of the static memory apparatus.
2. Description of Related Art
Referring to FIG. 1, FIG. 1 is a block diagram of a conventional static memory apparatus. A static memory apparatus 100 is a static random access memory apparatus, which includes a plurality of memory cells 111-11M, a plurality of dummy memory cells 121-122, and a sense amplifier 130. The memory cells 111-11M form a memory array 110 and are coupled to the sense amplifier 130 via bit lines BL1 and BL1B. A dummy bit line DBL coupled to the dummy memory cells 121-122 is connected with an input end of an inverter INV1, and an output end of the inverter INV1 is coupled to the sense amplifier 130 and provides an enable signal EN for enabling a sensing and amplifying operation of the sense amplifier 130.
When the static memory apparatus 100 executes a data reading operation, a voltage level of a signal transmitted by the dummy bit line DBL is lowered correspondingly, and the sensing and amplifying operation of the sense amplifier 130 is enabled by the enable signal EN that is raised correspondingly. Meanwhile, the sense amplifier 130 senses and amplifies a difference between signals on the bit lines BL1 and BL1B, so as to obtain readout data.
However, when a process mismatch occurs on the static memory apparatus 100, a speed of change of the signal transmitted by the dummy bit line DBL may become far faster than a speed of change of the signals on the bit lines BL1 and BL1B. As a result, when the sense amplifier 130 is enabled, correct readout data cannot be obtained because the difference between the signals on the bit lines BL1 and the BL1B is smaller than an offset voltage of the sense amplifier. The above situation becomes worse when the static memory apparatus 100 receives an operating voltage of a lower voltage value.